Texas Instruments - Revision history

Anonymous Coward: /* 486DX, DX2, DX4 */

2014-05-22T00:11:19Z

‎486DX, DX2, DX4

Anonymous Coward: /* 486DX, DX2, DX4 = */

2014-05-22T00:06:52Z

‎486DX, DX2, DX4 =

Anonymous Coward at 00:06, 22 May 2014

2014-05-22T00:06:19Z

Michael Dale: Created page with "TX486DLC"

2014-05-10T12:08:16Z

Created page with "200px|thumb|TX486DLC"

New page

[[File:Texas_Instruments_TX486DLC-E-40GA.JPG|200px|thumb|TX486DLC]]

@@ Line 13: / Line 13: @@
 == 486DX, DX2, DX4 ==
-Currently not much is known about the internals of these chips, except that they have 8kb internal cache. They were most likely derived from the 486SXL 168-pin version, which in turn was derived from the Cyrix 486DLC. These were not clones of Cyrix chips, as at this point relations between the two companies were on the rocks.
+Currently not much is known about the internals of these chips, except that they have 8kb internal cache. They were most likely derived from the 486SXL 168-pin version, which in turn was derived from the Cyrix 486DLC. These were not exact clones of Cyrix chips, as at this point relations between the two companies were on the rocks.
 == 5x86==
 Although never released, prototypes of this chip are known to exist. Not much is known except that they were rated for 133MHz. They were most likely designed in house and based on TIs modified Cyrix design. Around this time, TI left the x86 CPU business.

@@ Line 12: / Line 12: @@
 After falling out of favour with Cyrix, TI continued to produce modified DLC chips with 8kb cache. Other than the larger cache and a minor change to the control register these chips are more or less the same as the Cyrix chips. The larger cache does provide a small increase in performance. They were also produced in clock doubled versions (SXL2 and SXLC2). SXL chips were available in both 132-pin and 168-pin packages for 386DX and 486SX busses respectively. The SXLC chips were the 16-bit 386SX parts. Speeds ranged from 40 to 66MHz. Clock doubling circuitry is present in all chips (even the ones that are supposedly not clock doubled) and can be enabled using CPU registers. Clock doubling and cache are disabled on all chips by default
-== 486DX, DX2, DX4 ===
+== 486DX, DX2, DX4 ==
 Currently not much is known about the internals of these chips, except that they have 8kb internal cache. They were most likely derived from the 486SXL 168-pin version, which in turn was derived from the Cyrix 486DLC. These were not clones of Cyrix chips, as at this point relations between the two companies were on the rocks.
 == 5x86==
 Although never released, prototypes of this chip are known to exist. Not much is known except that they were rated for 133MHz. They were most likely designed in house and based on TIs modified Cyrix design. Around this time, TI left the x86 CPU business.

← Older revision		Revision as of 00:06, 22 May 2014
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	[[File:Texas_Instruments_TX486DLC-E-40GA.JPG\|200px\|thumb\|TX486DLC]]		[[File:Texas_Instruments_TX486DLC-E-40GA.JPG\|200px\|thumb\|TX486DLC]]
		+
		+	=== Texas Instruments ===
		+
		+	Texas Instruments initially did not design their own x86 CPUs, but acted as a second source for Cyrix as they did not have their own fabrication facilities.
		+
		+	== 486SLC/DLC ==
		+
		+	These chips were identical in every way to the Cyrix 486SLC and DLC chips. Hybrid 386/486 design, 386 bus compatible and 1kb internal cache.
		+
		+	== 486SXL/SXLC ==
		+	After falling out of favour with Cyrix, TI continued to produce modified DLC chips with 8kb cache. Other than the larger cache and a minor change to the control register these chips are more or less the same as the Cyrix chips. The larger cache does provide a small increase in performance. They were also produced in clock doubled versions (SXL2 and SXLC2). SXL chips were available in both 132-pin and 168-pin packages for 386DX and 486SX busses respectively. The SXLC chips were the 16-bit 386SX parts. Speeds ranged from 40 to 66MHz. Clock doubling circuitry is present in all chips (even the ones that are supposedly not clock doubled) and can be enabled using CPU registers. Clock doubling and cache are disabled on all chips by default
		+
		+	== 486DX, DX2, DX4 ===
		+	Currently not much is known about the internals of these chips, except that they have 8kb internal cache. They were most likely derived from the 486SXL 168-pin version, which in turn was derived from the Cyrix 486DLC. These were not clones of Cyrix chips, as at this point relations between the two companies were on the rocks.
		+
		+	== 5x86==
		+	Although never released, prototypes of this chip are known to exist. Not much is known except that they were rated for 133MHz. They were most likely designed in house and based on TIs modified Cyrix design. Around this time, TI left the x86 CPU business.